EMV Level 1 Software Library

The EMV Level 1 standard is a key global payment industry specification that defines the electrical, and physical interface between credit and debit cards and the payment terminal. NMI's new EMVL1.LIB Software Library for embedded systems has been developed to speed up your time to market and minimize the risk and cost of testing and certification.

The software library is designed to provide a compact, portable software solution for the implementation of the terminal requirements of EMV Book 1 (Version 4.3) and the smart card interface requirements of ISO 7816.

Key Highlights

  • Supports a growing number of smartcard interfaces including 5V, 3V and 1.8V
  • Provides SPI interfaces and serial port control
  • On board and off board clock support
  • Developed in strict ANSI C
  • Proven library on everything from a PIC to an ARM9
  • Fully tested library - ready for formal certification in your design
  • Full software and hardware support
  • EMVCo certified test equipment and software

EMV Level 1 Software Library Architecture

Level 1 Library Software Diagram

Five major functional layers are provided in the architecture of EMVL1.LIB:

1. Message Interface Layer
Interfaces with the EMV Level 2 Kernel message interface, or alternatively operates in a looped back mode which is required to allow testing.

2. Transport Protocol Layer
Manages the EMV features in ADPU mode including the formatting of ADPUs, and card reject timing settings which are numerous and ultra-critical.

3. Card Protocol Layer
Provides the T=0 and T=1 blocks which manage the ISO 7816 card protocols. These protocols operate in very distinct ways; T=0 is a byte oriented protocol and T=1 is a block oriented protocol. The ATR block determines card timing and the card protocol to be used (T=0 or T=1).

4. Chipset Virtualization Layer
Interprets the differing HALs and provides a common interface between to the Card Protocol Layer above. 

5. Hardware Abstraction Layer (HAL)
The HAL provides the analogue interface to the selected SMART Card IC. There is also a Customer Provided Hardware Abstraction block which provides interface to the customer’s selected processor for clock generation and timing, SPI interface, or serial interface (as necessary).

Supported Interfaces

Supported Secure Processors with built in Smart Card Interface

  • Maxim 32550 (Lighthouse)
  • Atmel AT91S051

Supported Smart Card Interface Chip Sets for EMVCo Contact Level 1

  • DS8204 (Maxim and others)
  • Linear technology LTC4556
  • NXP TDA8034HN
  • On Semicounductor NCN6001

Supported Contactless Transceiver Chip Sets for EMVCo Contactless Level 1

  • NXP CLRC663
  • With more soon to follow